Notes on Electronics Convos


gates in a circle, gate delay depends on temp and voltage, this sets the least count to something like 100 ps. There is a circuit that senses the phase of an external clock and adjusts the voltage to keep the ring in synch with the external clock. when clocks are out of sync, the chip indicates that in a bit and that bit is added to the output stream. the changes on the bit are not strictly syncronous with the condition of the clock sync, there may be a few triggers plus or minus between the indication of the bit vs. the sync condition under which the data were recorded.

Resolution could be worse when unlocked. He has seen factors of 5 to 8. This even though unlocked, the clock period should only change by 10% or so.

the unlocked state is unrecoverable. the meanderings of the period while lock is being sought is not recorded anywhere.

He recommends looking at the correlation of unlocked state and high rate. He has been able to knock a chip out of lock by putting in 20 MHz rate.


Had not heard of the missing bit on the DAC problem. If we get a board to him he will have a look.


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